Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach

Reconfigurable Optical Wireless Switches for on-chip Interconnection

4 × 4 Integrated Switches Based on On-Chip Wireless Connection through Optical Phased Arrays

Integrated Optical Phased Arrays for on-Chip Communication

Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations

Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs

The challenge of classification confidence estimation in dynamically-adaptive neural networks

Exploring Process-Voltage-Temperature Variations Impact on 4T1R Multiplexers for Energy-aware Resistive RAM-based FPGAs

On-chip wireless interconnection through reconfigurable optical phased arrays

An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform

Cost-effective and flexible asynchronous interconnect technology for GALS systems

Design of reconfigurable on-chip wireless interconnections through Optical Phased Arrays

Comparative Analysis and Optimization of the SystemC-AMS Analog Simulation Efficiency of Resistive Crossbar Arrays

Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited)

PSION+: combining logical topology and physical layout optimization for Wavelength-Routed ONoCs

Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator

An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing

A Low-latency and flexible tdm noc for strong isolation in security-critical systems